Considering eFPGA? Here’s What You Need to Know First
March 12, 2021
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Have you ever spent months evaluating a new technology only to find out that it really wasn’t suited for the task in mind and wished someone had warned you up front?
It’s happened to all of us at some point in our careers and can lead to disappointment and wasted time. This article is geared to avoid those disappointments when trying to determine if the flexibility of RTL reconfigurability is right for your next chip.
The journey of exploring the use of embedded Field Programmable Grid Arrays (eFPGA) IP is very straight forward and can be rewarding, provided the benefits and trade-offs are understood before you start. The key to a productive journey is to use representative designs that enables chip customization that makes your chip attractive to more customers, extends the life-cycle of end systems, or supports proprietary “secret” algorithms.
If you’re coming from an ASIC background, the first trade-off to know is that reconfigurability takes more area than ASIC gates. Starting with an ASIC design for an eval and comparing it in eFPGA is not the right comparison. Why start with a fixed function and then layer it over a fabric with reconfigurable overhead? ASIC gates will win the PPA comparison every time and is not representative of the flexibility eFPGA provides.
If you’re coming from an FPGA background and moving to an ASIC yet want to retain some FPGA functionality, you’d expect to get similar performance results in the same process node. That is unlikely to happen. Not because the eFPGA technology is not good, but because FPGA companies use a performance-tuned process and power their chips at a higher voltage than what the foundries support in their standard ASIC processes. So, if you’re barely meeting timing in an FPGA at 28nm, for example, be prepared to need to drop to the next process node to get similar performance or speed bin your ASICs and use only fast-fast processed wafers in the same process node.
Use of eFPGA is gaining moment across a number of market segments including 5G, SmartNics, Smart Switches, computation storage and even MCUs. Its flexibility, ability to support more compute parallelism and end-user customization post-silicon will become a mainstream requirement for systems companies. By knowing what to expect from eFPGA IP, you can make much more intelligent decisions in considering where you place reconfigurability in your chip architecture and reach satisfactory results with your evaluation.
If you have an idea about taking this eval journey, we’re more than happy to help you navigate through it.
Andy is responsible for Flex Logix’s EFLX and nnMAX IP. BS Chemical Engineering, Arizona State University. Over 20 years of sales and sales management experience starting as Account Sales Manager at Motorola Semiconductor then Director Strategic Accounts at ARM. Moved to ARC as VP Sales, North America. When Virage acquired ARC, became VP Global Accounts and lead worldwide sales effort for ARC. More on Andy can be found on the company website.
