Product of the Week: Lattice Semiconductor’s Lattice Nexus™ 2 Next-Gen Small FPGA Platform
December 10, 2024
Blog
Video processing, communication, and machine learning inferencing applications are often deployed across a range of industries and tasked with managing edge computing workloads requiring large memories, DSP resources, and a variety of high bandwidth interfaces. To support these applications, a next-generation small FPGA platform offers reconfigurability, high performance, and the ability to integrate advanced resources in a compact form factor.
The Lattice Nexus™ 2 is a low-power small FPGA platform from Lattice Semiconductor built on a 16 nm FinFET TSMC process technology and made up of 65k to 220k system logic cells, 120 to 520 multipliers (18 × 18) in sysDSP™ blocks, and 4 to 12 Mb of embedded memory (EBR).
Additionally, the Lattice Nexus™ 2 also supports the first family based on the platform, the Lattice Certus™-N2 general-purpose FPGAs, which are ideal for edge compute workloads. They support a wide range of I/O (with support for 3.3 V I/O) and feature 16G SERDES that support multiple protocols like 10G Ethernet and PCIe Gen 4.
The Lattice Nexus™ 2 in Action
For external memory interface support, the small FPGA platform features DDR4/LPDDR4 at up to 2400 Mbps data rate, DDR3L at up to 1866 Mbps data rate, and a hardened DFI (DDR PHY Interface) training layer.
Expanding on the high-speed communication features, the platform’s 16G SERDES and hardened PCIe Gen 1/2/3/4 are accompanied by 2-8 SERDES with up to 4.5 Gbps per lane of hardened MIPI D-PHY, and up to 3.5 Gbps or 7.98 Gbps per trio of hardened MIPI C-PHY.
In addition to the SERDES and hardened interfaces, the Lattice Nexus 2 has up to 349 configurable input/output pins, some for high-speed, low-voltage operations (High Performance, HP) and some for broader voltage compatibility (Wide Range, WR). The FPGA also supports 1.8 Gbps of Soft MIPI D-PHY, 1.6 Gbps of LVDS, and 3.3 V support.
The FPGA solution also supports a wide range of security features:
- AES-256-GCM encryption
- Up to ECDSA-521 and RSA4096 authentication
- Anti-tamper and PUF/Unique ID
- User data encryption
- Side channel resistance
- TRNG (True Random Number Generator)
Getting Started with the Lattice Nexus™ 2
The Lattice Nexus 2 platform-based devices support the Lattice Radiant™ integrated design software environment, a development tool for FPGA design, simulation, and implementation.
Lattice Nexus 2 devices also support a synthesis library of logic synthesis tools. According to the company, “Radiant uses synthesis tool output along with constraints from its floor planning tools to place and route the user design in Lattice Nexus 2 devices. The tool extracts timing from the routing and back-annotates it into the design for timing verification.”
Lattice Semiconductor also provides pre-engineered IP (Intellectual Property) modules for Lattice Nexus 2 families.
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