Breker Verification Systems, a provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), introduced its RISC-V TrekApp. The app is an automated test content generator for RISC-V system integration testing.

RISC-V TrekApp targets complex verification challenges and increases coverage by executing unpredictable corner-case scenarios without the need for manually developed test content. It  works with existing universal verification methodology (UVM) and SoC verification environments and does not require the user to learn the PSS language.

 "RISC-V excels in enabling new and innovative designs, creating verification opportunities for system integration," CEO of Breker Adnan Hamid, said in a press release.

The RISC-V TrekApp was developed in cooperation with SiFive, the a provider of commercial RISC-V processor IP and silicon solutions. It is also in use by multiple processor developers to test the integration of their custom devices.

RISC-V TrekApp results can be combined with general functional verification tests written in PSS, SystemVerilog, UVM, SystemC and C/C++ for a complete, cross-coverage test environment. It does not require knowledge of PSS, SystemVerilog or UVM languages and may be used in a fully automated fashion.

Features include interrupt mechanism testing, modular instruction extension verification, and links to multiple compliance test suites. A comprehensive full debug environment highlights tests that fail, including memory map and key register detail, and interfaces with common debuggers such as Synopsys' Verdi SoC Debug Platform for extended analysis.

Breker Verification Systems, a provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), introduced its RISC-V TrekApp. The app is an automated test content generator for RISC-V system integration testing.

RISC-V TrekApp targets complex verification challenges and increases coverage by executing unpredictable corner-case scenarios without the need for manually developed test content. It  works with existing universal verification methodology (UVM) and SoC verification environments and does not require the user to learn the PSS language.

 "RISC-V excels in enabling new and innovative designs, creating verification opportunities for system integration," CEO of Breker Adnan Hamid, said in a press release.

The RISC-V TrekApp was developed in cooperation with SiFive, the a provider of commercial RISC-V processor IP and silicon solutions. It is also in use by multiple processor developers to test the integration of their custom devices.

RISC-V TrekApp results can be combined with general functional verification tests written in PSS, SystemVerilog, UVM, SystemC and C/C++ for a complete, cross-coverage test environment. It does not require knowledge of PSS, SystemVerilog or UVM languages and may be used in a fully automated fashion.

Features include interrupt mechanism testing, modular instruction extension verification, and links to multiple compliance test suites. A comprehensive full debug environment highlights tests that fail, including memory map and key register detail, and interfaces with common debuggers such as Synopsys' Verdi SoC Debug Platform for extended analysis.

For more information, visit www.BrekerSystems.com/