NSITEXE, Kyoto Microcomputer, Codeplay Software Are Bringing Open Standards Programming to RISC-V Vector Processor for HPC and AI Systems
November 03, 2020
Implementing OpenCL and SYCL for the popular RISC-V processors will make it ideal to port existing HPC and AI software for embedded systems.
Codeplay Software announced that software developers working on HPC and AI for embedded systems will be able to take advantage of industry defined open standards from The Khronos Group on RISC-V architectures. The advantage is thanks to Japan’s New Energy and Industrial Technology Development Organization (“NEDO”) project in which NSITEXE and Kyoto Microcomputer are participating.
NSITEXE and KMC have ordered an implementation of LLVM for RISC-V Vector Extension Processor (“RVV”), Codeplay’s ComputeAorta and ComputeCpp, and implementations of OpenCL and SYCL open standards. In the NEDO project, as a research, NSITEXE develops OpenCL and SYCL compilers from LLVM to utilize RVV, and KMC implements vector syntax to utilize RVV efficiently based on LLVM and Clang. These research developments will contribute to RISC-V community to support open-standard technologies.
By porting Codeplay’s OpenCL and SYCL open standards products, developers targeting the RVV for AI accelerators will be able to program RISC-V’s open hardware implementations using familiar C++, port existing code from other AI systems and take advantage of an extensive ecosystem of tools, libraries, training, and skilled talent. Applications using this architecture range from high performance computing, automotive, and machine learning.
The development is being defined by NSITEXE and KMC, with funding from NEDO. The motivation is to develop next-generation computing technologies for AI chips that enable highly efficient and high-speed processing to solve some of the world’s most complex challenges, from self-driving vehicles to climate change.
For more information, visit: https://codeplay.com/portal/press-releases/2020/10/29/nsitexe-kyoto-microcomputer-and-codeplay-software-are-bringing-open-standards-programming-to-risc-v-vector-processor-for-hpc-and-ai-systems.html
Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.
She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.
Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
