Uppsala and Gothenburg, Sweden. IAR Systems and Gaisler are partnering on an IAR Embedded Workbench for RISC-V (IAR I-jet), a comprehensive development toolchain assisting engineers with an abundance of resources tied into one simplistic development platform. The workbench includes many debugging and assessment protocols for code and data breakpoints, as well as runtime stack analysis, call stack visualization, and code coverage analysis. The IAR I-jet is an economical debug interface with the Noel-V processor from Gaisler.

RISC-V Summit, San Jose. Solid Sands will be announcing it has been invited to the RISC-V community as a strategic member at the RISC-V Summit. While attending the show, industry insiders will learn Solid Sands expertise on how to qualify C and C++ standard libraries for safety-critical applications.

RISC-V Summit, San Jose. Microchip worked with NASA and the aerospace and defense industry to develop a RISC-V-based High-Performance Spaceflight Computing (HPSC) processor that is being presented at the RISC-V Summit. Microchip is also promoting its PolarFire 2 FPGA silicon platform and RISC-V-based processor subsystem with a software suite roadmap at the Summit.

RISC-V Summit, San Jose. Ashling is showcasing its Vitra-XS, a debug and trace probe for integrated design with support for RISC-V and Arm platforms. Ashling developed the Vitra-XS to collaborate with Ashling’s RiscFree Eclipse based IDE & Debugger utilizing USB 3.0, 38-way Mictor target connector, 512 MB of on-board trace storage, RISC-V debug & trace standards E-Trace and N-Trace, and Arm CoreSight debug & trace standards SWD, DAP, ETM, PTM, STM, and CTI.

RISC-V Summit, San Jose. Imperas Software Ltd., announced that Imagination Technologies will utilize the Imperas model IMG RTXM-2200, from Imagination’s RISC-V Catapult family, as a solution for software design in virtual platforms and EDA environments. The IMG RTXM-2200 is a scalable real time deterministic 32 bit embedded CPU developed for commercially available components.

 

RISC-V Summit, San Jose. Siemens Digital Industries Software announced that its security and cloud enabled Sokol Flex OS software, centered around the open-source Yocto Project industry standard, supports RISC-V embedded advancement with its customizable Linux platforms for the RISC-V architecture. “Siemens continues to show leadership within the RISC-V ecosystem with the launch of Sokol Flex OS for RISC-V,” said Krishnakumar Ramamoorthi, senior product marketing manager of Microchip Technology's FPGA business unit.

RISC-V Summit, San Jose. MIPS has designated Imperas to deliver flexible framework RISC-V processor verification tools to simplistically adapt from issue recognition and debug resolution in a testbench ecosystem consistent with the SystemVerilog EDA tools. The provided tools support the open standard RVVI (RISC-V Verification Interface) with the ability to communicate with a processor.