Imperas Software Ltd and Synopsys, Inc. announced a collaboration to accelerate verification of RISC-V processors utilizing ImperasDV verification platforms, and Synopsys' VCS simulation and Verdi debug tools. The partnership will ease time constraints by streamlining RISC-V verification tasks applying to components supplied by both partners.

Oxford, United Kingdom. Imperas Software Ltd. revised its ImperasDV for maintaining the expansion of RISC-V verification supporting both RTL bug detection and analysis while collaborating with design flow implementation in EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Imperas leverages RISC-V for its ability to be customized for specific industry needs. “RISC-V offers new freedoms in design flexibility which is driving a new wave of innovation across the semiconductor industry in almost all market segments,” said Larry Lapides, VP of Sales at Imperas Software Ltd.

RISC-V Summit, San Jose. Imperas Software Ltd., announced that Imagination Technologies will utilize the Imperas model IMG RTXM-2200, from Imagination’s RISC-V Catapult family, as a solution for software design in virtual platforms and EDA environments. The IMG RTXM-2200 is a scalable real time deterministic 32 bit embedded CPU developed for commercially available components.

 

RISC-V Summit, San Jose. MIPS has designated Imperas to deliver flexible framework RISC-V processor verification tools to simplistically adapt from issue recognition and debug resolution in a testbench ecosystem consistent with the SystemVerilog EDA tools. The provided tools support the open standard RVVI (RISC-V Verification Interface) with the ability to communicate with a processor.

Imperas Software Ltd announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts.

Imperas Software Ltd., announced that NSITEXE, Inc., a group company of the DENSO Corporation that develops and sells high-performance semiconductor IP for automotive applications, has selected ImperasDV for its advanced RISC-V processor hardware design verification.

RISC-V is known as an open-standard instruction set architecture (ISA) whose base instructions have been frozen to minimize complexity. But more recently it has added a wide range of custom extensions and enhancements that are making it increasingly popular amongst SoC designers building application-specific systems.