It’s almost time for the RISC-V Summit North America again and Embedded Computing Design will be there to bring back all the innovation, execution and application you want to know. Let’s take a quick look at what will be going on in the conference session and a few things that we’re particularly interested in attending.

Microchip is packing up in Chandler, Arizona and will start its trip to the RISC-V Summit in Santa Clara, California, November 7^th and 8^th, 2023, and November 6 being Member Day. Microchip will be demonstrating its market leading FPGA solutions for the intelligent edge and how it leverages the RISC-V ISA to design heterogenous processing architectures for non-proprietary instruction set architectures.

Arteris, Inc. announced Tenstorrent is leveraging its Ncore and FlexNoC interconnect IP for its AI chiplet systems. The results is a flexible network-on-chip (NoC) interconnect for next generation AI solutions. The combination of Tenstorrent’s AI chiplet’s and RISC-V's openness are tailored specifically to users’ requirements.

Imperas Software Ltd and Synopsys, Inc. announced a collaboration to accelerate verification of RISC-V processors utilizing ImperasDV verification platforms, and Synopsys' VCS simulation and Verdi debug tools. The partnership will ease time constraints by streamlining RISC-V verification tasks applying to components supplied by both partners.

Nuremberg, Germany. Announced during embedded world 2023, Ashling’s RiscFree SDK will deliver software development support for Imagination’s Catapult RISC-V-based IP cores.  The collaboration between the two companies produced the RTXM-2200 which is the first industrial licensable CPU IP from the RISC-V Catapult family. Highlights include a real-time, scalable, 32-bit integrated design with Imagination’s expertise in CPU development.

RISC-V Summit, San Jose. during the RISC-V Summit 2022, StarFive Technology’s Director of Software Engineering, Chin Liang, presented on StarFice's work toward developing the next generation of the RISC-V ecosystem. In Liang’s lecture, you will learn in-depth knowledge of RISC-V architecture, tools, and Linux distribution. See how you can use the knowedge gained for solutions in your designs.

RISC-V Summit, San Jose. Ventana Micro Systems Inc.’s founder and CEO Balaji Baktha will present Ventana’s Veyron family at his RISC-V Summit keynote address. The standards based Veyron V1 is a RISC-V processor that will come in chiplets and IP assisting in single thread performance targeting solutions for data centers, automotive, 5G, AI, and client applications.