CAST
Woodcliff Lake, NJ 07677 [email protected]
+1 201.391.8300
https://www.cast-inc.com/
The Road to RISC-V Summit: CAST to Highlight 32-bit Solutions in Functional Safety and Ultra-Low Power - Blog
October 18, 2024During this year’s RISC-V Summit, CAST will be in booth S13 demonstrating its processors offered in ASICs or FPGAs for embedded systems, Internet of Things edge devices, industrial control systems, automotive, and aerospace applications. CAST’s RISC-V IP core line features processors focused on competitive 32-bit solutions in Functional Safety and Ultra-Low Power.
CAST and Ubilite Team-Up at the RISC-V Summit - News
November 08, 2023RISC-V Summit, Santa Clara, California. According to CAST, Ubilite, Inc. has licensed a RISC-V IP core for its next generation of Wi-Fi chipsets with an ultra-low power consumption rivaling Bluetooth Low Energy. Peter Gammel, Chief Executive Officer, Ubilite said, “We expect the RISC-V processor core we’ve licensed from CAST to help us maintain — and extend — the advantages of our low-power Wi-Fi SoCs over competing IoT products.”
embedded world 2023 Best in Show Winners: Processing & IP - Product
March 13, 2023Winners have been chosen based on a 15-point rubric that considers solutions’ Design Excellence (5 points), Relative Performance (5 points), and Market Impact/Disruption (5 points).
Best in Show Nominee: CAST's EMSA5-FS Functional Safety Embedded RISC-V Processor - Product
March 09, 2023The EMSA5-FS is a 32-bit, in-order, single-issue, five-stage pipeline processor supporting the open standard RISC-V ISA. Its fail-safe features include built-in triple or double modular redundancy, error correction code bus protection, a configurable memory protection unit, privileged operation modes, and Reset and Safety Manager Modules.
Fraunhofer IPMS, CAST to Launch a New Processor IP for Edge AI Applications - Blog
December 09, 2021All the technological advancements in developing efficient processor cores have led several semiconductor players to design processor IP using open-source instruction set architecture.