The Road to RISC-V Summit: CAST to Highlight 32-bit Solutions in Functional Safety and Ultra-Low Power
October 18, 2024
Blog
During this year’s RISC-V Summit, CAST will be in booth S13 demonstrating its processors offered in ASICs or FPGAs for embedded systems, Internet of Things edge devices, industrial control systems, automotive, and aerospace applications. CAST’s RISC-V IP core line features processors focused on competitive 32-bit solutions in Functional Safety and Ultra-Low Power.
The EMSA5-FS 32-bit Embedded RISC-V Functional Safety Processor is an ISO26262 ASIL D Ready IP core that offers:
- Single-issue, in-order, 5-stage pipeline processor with an optional L0 instruction cache
- Extensive RV32 base integer or base embedded ISA options, including full, partial, or optional support for RV32[I/E][C][M][F][D][A][Zicsr][Zifencei] and Vector Instructions
- Fail-safe design features, including Dual Modular
- Redundancy (DMR) in Lockstep or triple (TMR), Error Correcting Code (ECC), and sample Reset and Safety Manager modules
- A complete ISO 26262 Certification Package, including a Safety Manual (SAM) and a Failure Modes, Effects and Diagnostics Analysis (FMEDA) document
The EMSA5-FS's performance and resource requirements vary with its configuration and ASIC or FPGA implementation. DMR versions start at 40k gates, and TMR at 60k. On advanced processor nodes, EMSA5-FS performance can surpass frequencies over 1GHz.
CAST’s 32-bit RISC-V low-power processors for embedded applications require a small silicon footprint for minimal leakage and dynamic CPU power. They also employ advanced power management techniques such as dynamic clock gating and clock frequency scaling. RISC-V support includes RV32 base integer or base embedded ISA and extensions, including full, partial, or optional support for RV32[I/E][C][M][F][D][A][N][Zicsr][Zifencei] and Vector Instructions.
CAST processors are available in ASICs or FPGAs for embedded systems, Internet of Things edge devices, industrial control systems, automotive and aerospace applications, and more. CAST processors feature:
- Extensive and configurable RISC-V ISA and feature support;
- High quality and reliability through best design and coding practices, and rigorous verification and testing;
- Royalty-free and other flexible licensing options;
- Design for reusability with integration and complete deliverables;
- Companion IP cores are available for bus fabrics, peripherals, networking, security, and hardware accelerators for compression and other critical functions.
The RISC-V IP core line features processors focused on 32-bit solutions in two key areas: Functional Safety and Ultra-Low Power. Further, the 32-bit RISC-V low-power processors for embedded applications require a small silicon footprint for low leakage and vital CPU power. They also employ advanced power management techniques such as dynamic clock gating and clock frequency scaling. For example, the BA51 Ultra-Low-Power Deeply Embedded RISC-V processor:
- has a single-issue, in-order, 2-stage pipeline;
- uses from 16K gates;
- runs over over 500 MHz (16nm) and achieves 400 Coremarks/MHz;
- is optionally equipped with L0 instruction and data caches.
The BA53 Low-Power Deeply Embedded RISC-V processor:
- has a single-issue, in-order, 5-stage pipeline;
- uses from 30k gates;
- runs over 1GHz (22nm) and achieves 2.53 Coremarks/MHz;
- is optionally equipped with L0 instruction and data caches.
CAST RISC-V processor cores are available in Verilog source code for ASICs or as netlists for FPGA devices. They use standard AMBA® interfaces for integration and are compatible with open-source and commercial RISC-V development tools. CAST offers flexible licensing options, including royalty-free choices. You can license a processor independently or with a platform that includes bus fabric, peripherals like GPIO, UART, I2C, and memory controllers. CAST also provides custom integration with other IP cores, including a range of automotive IPs.
Visit the CAST at booth S13 at the RISC-V Summit or check out the RISC-V Family web page for detailed comparisons in our datasheet.
For more information, visit cast-inc.com/processors/risc-v.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
