Using emulation to verify today's complex designs

By Lauro Rizzatti

Marketing Consultant

RIZZATTI LLC

June 01, 2010

Increasing time-to-market pressures, along with escalating hardware/software integration and quality concerns imposed on engineering teams, make the v...

 

Such multilevel debugging methodology would not be possible with software simulators because they are too slow to effectively execute embedded software. Likewise, the same methodology would not be possible with FPGA-based prototypes since they lack visibility and access into the design to trace hardware bugs.

New emulation platforms

New emulation systems (Figure 1) are now replacing traditional big-box versions because they run faster and are easier to use and less expensive. They also consume a fraction of the power dissipated by bigger versions, require less space, and weigh less.

 

Figure 1: New cost-effective emulators offer performance, debug capabilities, and design capacity to make them ideal for today’s large SoC designs.


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These highly scalable, cost-effective tools are capable of handling up to 1 billion ASIC gates, boast fast compile time and emulation speed, offer a powerful debug environment, and support multiple concurrent users, all packaged within an environmentally friendly footprint.

What’s more, emulators can be deployed as emulation systems driven by a physical target system or as acceleration systems driven by a virtual, software-based test bench. Typical performance is approximately 10 MHz on a 10 million gate design and a top speed of 30 MHz on smaller designs. In these examples, emulators would process 10 seconds of real time in less than two minutes. Fast compile times range from 5 to 30 million gates per hour on PC farms, depending on the size of the farm and the design’s complexity.

Increasing time-to-market pressures, along with escalating hardware/software integration and quality concerns imposed on engineering teams, make the verification process a strategically important step in chip design. A new generation of cost-effective emulators such as EVE’s ZeBu-Server (for Zero Bugs) capable of handling up to 1 billion or more ASIC gates at high speeds reaching several megahertz provides a great choice for large designs.

Lauro Rizzatti is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, and has held responsibilities in top management, product marketing, technical marketing, and engineering.

EVE-USA
408-457-3201

[email protected]
www.eve-team.com

 

Lauro Rizzatti (EVE-USA)

Dr. Lauro Rizzatti is a true global citizen whose 30-year career in the Electronic Design Automation (EDA) and Automatic Test Equipment (ATE) industries has spanned the globe enabling him to reside in places like the United States, Europe, the Middle East, Japan, and the Pacific Rim. While cultivating his affinity for living abroad, he held management positions of significant responsibility. His expertise in product marketing, technical marketing and engineering made him an attractive candidate.

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