Ventana Releases the Veyron V1, a Data Center Class RISC-V CPU
December 12, 2022
News
CUPERTINO, Calif. Ventana Micro Systems Inc. released its standards-based data center class of RISC-V computing, the Veyron V1. The Veyron V1 is a member of Ventana’s Veyron family of high-performing RISC-V processors. According to Ventana, Founder and CEO Balaji Baktha will speak on the many features of the Veyron family during his RISC-V Summit keynote. Highlights are expected to include, an eight wide and aggressive out-of-order pipeline, 3.6GHz, 5nm process technology, 16 cores per cluster, high core count multi-cluster scalability up to 128 cores, and 48MB of shared L3 cache per cluster.
“Our vision of delivering the highest performance RISC-V CPUs is helping to reshape next generation high performance open hardware architectures,” said Balaji Baktha, Founder and CEO of Ventana. The single thread performance is ideal for applications involving data centers, automotive, 5G, AI, and client applications.
The Veyron V1 also offers the benefits of:
- Advanced side channel attack mitigations
- Comprehensive RAS features
- Top-down performance tuning methodology
- Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP
- SDK released with necessary software already ported to Veyron
- Veyron V1 Development Platform available
The efficacy of the Veyon V1 along with RISC-V’s open architecture optimizes workloads for gains through domain specific acceleration to combat Moore’s Law and the emergent of energy and thermal restrictions for data centers. The Veyron V1 is delivered in the form of high performance chiplets and IP, that combined with RISC-V’s open and extensible architecture, enables customer innovation and workload optimization. This results in further workload efficiency gains through domain specific acceleration that will extend Moore’s Law to deal with the emerging energy and thermal constraints for data centers. Additional highlights of the Veyron V1 include:
- Advanced side channel attack mitigations
- Comprehensive RAS features
- Top-down performance tuning methodology
- Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP
- SDK released with necessary software already ported to Veyron
- Veyron V1 Development Platform available
Baktha continues, “Today, we have a significant first mover advantage by providing a platform that can allow customers to innovate and differentiate. Markets which require high performance compute such as Data Center, 5G, AI, Automotive, and Client will all benefit from our open standards-based, ultra low latency chiplet solution.
*Ventana Founder and CEO Balaji Baktha will make the public announcement during his RISC-V Summit keynote.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
