San Jose, California. Tessolve and Renesas collaborated to develop Tessolve’s SMARC SOM compatible with SMARC standard 2.1 and based on the RZ/V2H MPU leveraging four Arm Cortex-A55 CPU cores alongside two Cortex-R8 cores, one Cortex-M33, and an AI Accelerator (DRP-AI3) capable of eight TOPS/dense and 80 TOPS/sparse.