MIPI IP Portfolio Includes Design IP, Verification IP, Hardware Emulation and FPGA Prototyping Models, Post Silicon Validation IP.

A configurable bus functional model (BFM), protocol monitor, and library of integrated protocol checks come standard with SmartDV's Verification IP.

SmartDV's standard and custom protocol Design IP is optimized for high performance, low power and minimum area/gate count.

SmartDV Technologies introduced its new Design IP for DDR5 and LPDDR5 SDRAM controllers.

Multi-Year Agreements, New Customers in U.S., Japan, Europe, China, Korea Contribute to Success

VIP Ensures Thorough, Seamless Coverage-Driven Verification Flow Between Simulation, Emulation, Formal Verification.

Smart ViPDebug Demo will Highlight Ability to Reduce Debug Time through Linked Waveform, Transaction Database Views.