Monheim am Rhein, Germany – October 10th, 2022 – SEGGER announced native J-Link debug probe support for select use cases with the Cadence Tensilica Processor IP. The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), and also the Tensilica Fusion F1 DSP.

MONHEIM AM RHEIN, GERMANY. SEGGER has released the Device Support Kit (DSK) for its J-Link debug probes and Flasher in-circuit programmers that simplifies the process of supporting new devices on the popular development tools.

As part of a partnership with Geehy Semiconductor, SEGGER’s J-Link debug probes, as well as its family of Flasher in-circuit programmers, fully support the Geehy Polaris APM32 series MCU. Geehy and their customers now enjoy the benefits of J-Link Prime with these devices being supported right out of the box.

SEGGER’s BigFAT specification, which enables any third party to store files larger than 4 GB on standard FAT media, is now publicly available. This specification is not encumbered by any patents and can be used freely, along with the supporting tools.

SEGGER and Nuclei Technology, a China-based RISC-V processor IP and solution company, announced that the Nuclei Studio IDE now comes integrated with SEGGER's emRun runtime library.

SEGGER’s emRun++ is a C++ library fully compatible with the modern 2017 standard. It is used and proven in SEGGER’s multi-platform Embedded Studio IDE for RISC-V and Arm and is now available for licensing to toolchain vendors.