Semidynamics' RISC-V Technology Powers UPMEM’s Next-Gen AI Processing-in-Memory Chips
December 09, 2024
News
Barcelona, Spain. Semidynamics released information that UPMEM has selected Semidynamics as its core source for its next generation of LPDDR5X Processing in Memory device. By incorporating the Tensor Unit and Gazillion optimizer, the RISC-V architecture enables efficient integration of any AI or LLM models.
Roger Espasa, CEO of Semidynamics, added, “We are very happy to work with UPMEM and to support them with their Process in Memory approach. This is an extremely innovative way to enable deployment of Large Language AI models and we look forward to a long-term partnership with UPMEM.”
An internal bandwidth of 102.4GB/s, combined with a low energy data access of 1pJ/bit, and high performing processing capabilities (8 TFLOPs FP16/BF16, 16 TOPs int8) supports model inference abilities above the industrial average for a single chip.
Gilles Hamou, CEO of UPMEM, said, “Semidynamics GenAI compute IP combines the power and efficiency needed for our disruptive Processing In Memory DRAM chips for mobile. We also appreciate their use of RISC-V architecture as well as involvement in the RISC-V eco-system. Our combined technologies provide the only solution to be powerful enough and sufficiently energy and cost effective to compute most generative AI compute on the smartphone.”
For more information, visit semidynamics.com and upmem.com.
