New LPSRAMS from Alliance Memory Offer Integrated Error-Correction Code
January 31, 2023
News
Kirkland, Wash. Alliance Memory shared that it has extended its portfolio of low power asynchronous SRAM (LPSRAM) devices. The AS6CE1016A (1Mb) and AS6CE4016B (4Mb) integrate an error-correction code (ECC) for a more reliable LPSRAM When juxtaposed to previous-generation technology, the LPSRAM’s deliver upgraded failure in time (FIT), mean time to failure (MTTF), and characteristics with reduced soft error rates (SER).
Ideal for efficient power applications, both the 1Mb and 4Mb devices support 1-bit error correction per byte. Retaining data voltages are 1.5V at 1µA for the 1Mb AS6CE1016A and 2µA for the 4Mb AS6CE4016B. This means of support is required for battery backup nonvolatile memory applications while operating on a power supply of 2.7V to 3.6V. Alliance Memory has made sure all I/O’s are TTL compatible.
The optimized LPSRAM’s deliver the technology needed for autonomous industrial solutions including:
- control panels
- elevator systems
- printers
- calculators
- gaming machines
For more information, visit Alliance Memory.
Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.
He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.
Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.
