An Introduction Into NAND Flash Memory Systems

January 10, 2023

Blog

Since its initial appearance on the market in the 1980s, NAND flash has become a highly popular storage technology, found in memory cards, USB flash drives, and solid-state drives which power a wide range of consumer and industrial devices.

The global hunger for data and the increasingly connected world in which we live has driven a relentless demand for storage and, in line with the increasing performance and shrinking form factors of modern devices, pressure has also grown on the cost, density, and performance of NAND flash memory systems.

These pressures have driven an increase in the complexity of NAND flash systems accompanied by several challenges. The semiconductor technologies on which NAND flash is based are inherently unstable and suffer degradation with time and so require careful management, which is the role of the flash memory controller.

The memory controller is an often overlooked, yet crucial component of almost any NAND flash system, responsible for functions including error correction, mapping, garbage collection and, increasingly, data security. This article looks at how both NAND flash and controller technology have evolved in response to the challenges faced by these technologies in response to market demands for higher capacities, increased security, and lower cost.

A Brief Overview of NAND Flash Technology

NAND flash is a type of non-volatile storage technology which does not require power to retain data – although it does require power to program, erase, and read data.

The cells of a NAND flash memory are based on the floating gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), figure 1, a type of electrical switch where current flowing between two terminals, the Source and Drain, is controlled by a third terminal – the Control Gate.

Figure 1: Current flowing between the MOSFET Source and Drain is controlled by the Control Gate

A NAND memory cell is programmed by applying a high voltage to the Control Gate of the MOSFET. When sufficiently high, with both source and drain grounded, this voltage causes electrons in the channel to gain enough energy to overcome the oxide barrier, moving from the channel into the floating gate (FG). The FG is electrically isolated therefore this electric charge is stored permanently, even when power is removed. To erase the cell, a high voltage is applied to the substrate of the MOSFET while the Control Gate is grounded, extracting the electrons trapped in the FG, bringing the threshold voltage of the programmed cell back below zero.

NAND memory cells are read by applying a voltage between the control gate and source. With a programmed cell, no current can flow between source and drain while when the cell has been erased, current can flow.

A NAND flash cell must be erased before it can be written to and each erase operation causes damage to the cell, eventually wearing it out. Each cell therefore has a finite lifetime, known as the P/E cycle and is inherently unreliable. The effect is exacerbated by the fact that an individual cell cannot be erased, only blocks, made up of several pages which contain the cells, can be erased, while the writing operation happens on the page. When a cell’s information would change, it is written to another cell, leaving the cell with the old data marked as ‘ready for deletion’. When a whole block should be erased, the still ‘good’ data in that block is then moved elsewhere and the whole block is erased. This deterioration is also accelerated by heat generated during the NAND’s operation and 3D NAND, with its smaller cell structures, is particularly susceptible to these aging effects.

The Evolution of NAND Flash

With the cost per byte of NAND flash memory dictated by the number of bits stored on a given size of chip, several techniques have emerged to increase the storage density of NAND flash. Initial efforts to increase density by reducing the individual cell size were compromised by undesirable side effects, including larger leakage currents and higher error rates. Subsequent initiatives focused on increasing the number of bits that could be stored in each cell, although this technology also suffers from compromises, such as shorter lifetime, and higher error rates.

Modern flash memories achieve cost per byte reductions by using 3D NAND architectures, where multiple layers of memory cells create a three-dimensional structure within the silicon. 3D NAND memories offer significantly greater storage capacity and the shorter connections enabled by the layered structure supports faster data transfers, higher endurance, and lower power consumption. Most recent 3D flash memories use charge trap (CT) cell architectures which have several advantages when compared with FG cells, including higher P/E cycle endurance, lower power consumption, faster programming and reading. CT memories also enable higher scale at manufacturing although these advantages are offset by reduced data retention, especially at higher temperature.

The Flash Controller

A 3D NAND system relies heavily on its memory controller, figure 2, a key component which defines the overall quality of the flash, influencing its lifetime, data integrity and performance.

Fig 2: NAND Flash Controller Architecture

The controller ensures that data sent from the host to the NAND flash can be retrieved reliably and efficiently later, masking the inherent flash deficiencies discussed and its key functions include:

• Translation of the Read/Write/Status commands issued by the host into a format which can be understood by the NAND flash, including translating between different interfaces (e.g., SD, eMMC or SATA) and different NAND flashes (e.g., KIOXIA, Micron, Samsung).
• Mapping of the logical block addresses, (LBAs) of the host’s file system into addresses on the flash memory
• Detection and correction of errors within the NAND flash
• Implementation of appropriate digital security measures
• Flash Calibration

The Growing Demands Placed on NAND Flash Memory

With each new generation of flash, the demands on the controller increase, demanding more sophisticated and powerful hardware and software architectures. The controller implements a number of functions to ensure the reliable performance of the NAND flash memory and each of these core functions must adapt to these increasing demands.

Error Correction: As NAND flash integration sizes shrink and new technologies such as 3D NAND arrive on the market, flash error rates continue to grow and error correction requirements for flash memory controllers increase. Three independent factors are behind this increase in bit error numbers. As cells shrink, they store fewer electrons, making it harder to ascertain their value. The challenge is increased with each flash generation, as more bits are packed into a cell, leading to a reduction in voltage differences that indicate the state the cell is in. Finally, with higher cell densities, read and write operations on any individual cell have an increasing tendency to disturb the contents of its neighbouring cells.

This continued growth in error rates requires a corresponding increase in the error correction capabilities of the memory controller and error correction is now one of its most important tasks. Controllers must host more sophisticated error correction algorithms, presenting challenges when cost, form factor, and power consumption are considered.

Security: NAND flash memory is used in a wide variety of consumer and industrial products, including embedded IoT devices and, in our increasingly connected world, robust security measures are required at all vulnerable points in these applications, including the data storage system. Security measures have become increasingly granular, demanding specific features in the memory controller’s firmware and hardware which place additional demands on its processing resources - with a consequent trade-off against space, power, and performance.

Flash Calibration changes the reference voltage of a cell to eliminate or reduce bit errors. Cell threshold voltages can shift over time in response to factors such as program- and erase-cycling, read disturb, data retention, and temperature variation. Calibration is a time-consuming operation which can limit read performance if done too often and it is down to the controller to decide when to perform it, based upon the error rate of a given block or page.

Choose your NAND Flash Controller with Care

The global hunger for cheap, high-capacity data storage has driven significant innovation in NAND flash technology over the last decade. As NAND flash becomes denser and more sophisticated the demands on the flash memory controller are increasing. Each type of controller responds to these demands differently and, with a wide range of flash memory controllers on the market, it is essential to understand how each one compensates for the inherently unreliable nature of the NAND flash.