Embedded World 2022 Best in Show Winners: Processors & IP
June 17, 2022
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Winners have been chosen based on a 15-point rubric that considers solutions’ Design Excellence (5 points), Relative Performance (5 points), and Market Impact/Disruption (5 points).
The Embedded Computing Design editorial staff is pleased to present this year’s embedded world Best-in-Show winners in the Processors & IP category:
Codasip's Customizable Codasip L31
The L31 is a small, efficient 32-bit embedded RISC-V processor core aimed at embedded systems with more modest processing requirements.
The core has a 3-stage pipeline and has 32 general-purpose registers. Custom instructions can be created using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits. The core supports Tensor Flow Lite Micro for developing embedded AI applications such as neural networks.
Lattice Semiconductor's CertusPro-NX
The CertusPro™-NX family of low-power general purpose FPGAs featuring 10G SerDes, LPDDR4 memory interface support and up to 100k logic cells can be used in a wide range of applications across multiple markets.
It is built on the Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology, and offers small footprint package options as well as 0.8 and 1.0 mm ball-pitch package options. CertusPro-NX supports a variety of interfaces including PCI Express® (Gen1, Gen2, and Gen3), Ethernet (up to 10G), SLVS-EC, CoaXPress, eDP/DP, LVDS, Generic 8b10b, LVCMOS (0.9–3.3 V), and more.
Menta SAS's eFPGA SOFT IP
In addition to offering the eFPGA IP as a GDSII hard IP, Menta also provides eFPGA as soft RTL IP.
The IP hardening is then done by the customer. Menta delivers the first eFPGA soft IP in the semiconductor Market. The eFPGA Soft IP is available immediately and is compatible with any standard EDA tool flow. This new offering gives engineers greater flexibility in how they implement their SoC and ASIC designs.
