A growing number of embedded and IoT devices need more program memory than what can be implemented economically on-chip using embedded Flash or SRAM. For these designs, more and more designs are moving to eXecute-in-Place (XiP) operation in which code is executed directly from an external NOR Flash memory device, and in this way can achieve scalability for their system.

Most designers will typically choose a Quad Serial Peripheral Interface (SPI) memory for their XiP system since it’s the lowest cost option. However, depending on the specific application, a designer may have trouble meeting performance requirements when using a Quad device.

They can address this by making software optimizations, but such changes often require software teams to spend weeks or even months to optimize the design, and even then, the optimizations still might not be enough. It may ultimately be necessary to eliminate features from the design. Another option could be to crank up the clock speed of the processor to achieve the requisite performance, but that may provide diminishing returns and increase system energy consumption and potentially battery size and thus cost. And of course some designs already have their processor running at max clock speed, in which case it might be necessary to upgrade to a faster, more expensive processor.

An option that designers should consider is moving from a Quad SPI device to an Octal SPI device for their design. While the move won’t make a huge difference for all applications, there are some that will benefit significantly. The advantage is seen in those applications that are sensitive to the performance of the flash.

The simple way to predict this is by looking at the amount of traffic on the SPI bus. If your application is running mostly out of the cache, you won't see a lot of transactions on the bus. When you start seeing a lot of traffic/high utilization of the bus, that's when you know it's more reliant on the flash. If the bus is highly utilized, the gains from switching to an Octal device like Adesto’s EcoXiP are quite substantial. Ultimately this can translate to significant energy and cost savings.

We used a logic analyzer to measure the SPI bus utilization in Quad mode to see how it correlates with system speed-up when switching to an Octal device. We ran the CoreMark benchmark to generate more/less traffic on the bus by clearing the contents of the cache at fixed intervals (cache invalidations). These cache invalidations were designed to emulate real-time system scenarios where task-switches and interrupts are frequent. By making the intervals shorter and shorter, we increased the traffic on the bus.

You can see that there are areas where the difference between Quad and Octal performance is not that large, but then it swings upward. At that point, it’s worth considering the move to an Octal device. You can see the benefits when an application demonstrates 60 percent or above utilization of the SPI bus.

Power is an important consideration in many systems. We wanted to ensure that the extra performance that can be obtained by using an octal device is not traded off against higher system-level power consumption. We used the same setup to measure the power consumption of the NXP i.MX RT1050 MCU when running in eXecute-in-Place mode. We used the same technique of injecting cache invalidations at fixed intervals and measured the power of the MCU and the flash. The following graph shows that across all the scenarios that we tested, the Octal EcoXiP is more power efficient than a traditional Quad device. EcoXiP delivered a higher number of CoreMarks per mW in each of these scenarios. It is also interesting to note the power advantage of the EcoXiP increases with tougher workloads that have more cache misses and thereby more traffic on the SPI bus.

If you’re using a device like the NXP i.MX RT1050, you can easily swap out your Quad device with an Octal device, as the chip was smartly architected to support both.