CHIPS Alliance, presented OmniXtend advances at the RISC-V Summit earlier this month. Further,  it will collaborate with RISC-V International to standardize an open unified memory coherency bus leveraging OmniXtend to foster innovation for data-centric applications.

OmniXtend is a cache-coherency protocol architecture that exports Tilelink cache-coherence messages on the top of L2 ethernet frames.

"As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems," said chairman of the CHIPS Alliance and senior director at Western Digital Dr. Zvonimir Bandić, in a press release. "CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently.

“We see a unique opportunity because RISC-V is freely open, while other architectures don't open up the coherency bus, with RISC-V we can create an open unified memory standard to accelerate innovation for data-centric, heterogeneous applications."

Dr. Bandić presented during the session titled, "OmniXtend: Open Source Cache-coherence over Ethernet," which discussed the results of four four RISC-V nodes, each running four independent RISC-V harts, connecting via commercial ethernet switch, and establishing a ccNUMA (cache coherent non-uniform memory access) architecture.

For more information, visit https://chipsalliance.org/.