Software-Defined Radio (SDR) would be a great choice for mobile devices of all kinds if it weren't such a power hog. Can SDR fit in a more energy-efficient chipset? Here's the case for rethinking the architecture to fit a lower-power implementation.

For many companies already working with SDR implementations, the use of assembly code to program processors at low levels has proven critical to achieve required performance levels. However, using assembly programming has two major effects:

1. Code written for one processor cannot easily be moved to another or future generations of the same processor without a complete rewrite. Even the use of a cross-assembler results in poor performance translation. This has a significant impact on the portability of large software components, leading to cost and competitiveness issues.

2.  The creation of these assembly code programs takes a large amount of expert engineering time with a deep understanding of both the processor and algorithms being implemented. This in turn makes the methodology both expensive and time-consuming, delaying time to market.

MVR will only work commercially if the portability and programmability issues are solved. Emerging optimization techniques, including new technology from Sigmatix included in its MVR baseband platform (shown in Figure 2), open up the use of high-level languages in a high-performance manner. This technology leverages an understanding of processor hardware usually associated with synthesis technologies and applies this information to parallelize and tightly map algorithms onto the processor architecture. A system of C++ templates is used to code algorithm descriptions into a form that can leverage the facilities provided by the processors, achieving high-performance portability.

In this approach, protocol or baseband design engineers can use C code to describe their algorithm elements without considering the processor architecture. Processor engineers drive the construction of templates that provide raw data on the processor and leverage parts or all of the compiler technology that comes with it, as appropriate. An optimizer combines the two code bases, modifying the input code to make the best use of the target processor architecture to produce either raw assembly code or processed C code that includes intrinsics to guide a further compilation step. The binary code is then run against a cycle-approximate model of the processor, and analysis is performed to check for common performance issues that can result in a refinement in the code base.

MVR for the next generation

SDR has proven valuable for military and commercial wireless baseband implementations given the increased ease of use, multimode applications, and control versatility afforded by its use. However, its low-performance level compared to that of custom hardware has created a barrier to its proliferation in power-sensitive applications such as commercial cellular handsets. Furthermore, the lack of programmability and portability of higher-performing assembly code implementations detracts from its use in more general infrastructure applications.

MVR solves this problem by leveraging multiple dimensions of parallelism afforded by modern processor architectures to drive an order of magnitude performance improvement without a reduction in the positive benefits of software-based devices. By leveraging a methodology that retains performance in a portable and programmable fashion, MVR represents the future of next-generation baseband design.

Dave Kelf is the president and CEO of Sigmatix, Inc. After a number of years in DSP and communications semiconductor engineering roles at Plessey and Nortel, Dave worked in both sales and marketing at Cadence Design Systems, where he was responsible for the successful Verilog and VHDL verification product line. As VP of marketing at Co-Design Automation and then Synopsys, he oversaw the successful introduction and growth of SystemVerilog before running marketing for Novas Software (now Springsoft). Dave holds an MSc in Microelectronics and an MBA.

Phil Moorby is CTO of Sigmatix, Inc., and considered a semiconductor industry luminary. He is known as the inventor of the Verilog Hardware Description Language, for which he was bestowed the EDAC Phil Kaufmann Award in 2006. Phil cofounded Gateway Design Automation, one of the companies that formed Cadence Design Systems, and was appointed Fellow at Cadence. He also cofounded Synapix, Inc., a company focused on advanced video stream analysis. As Chief Scientist at Co-Design Automation, Phil was instrumental to the success of SystemVerilog. Drawing from his background in mathematics and performance software, he now leads the Sigmatix technology vision and development programs.

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