NASA Goes to SiFive for Future Space Missions

By Chad Cox

Production Editor

Embedded Computing Design

September 07, 2022

News

Image Courtesy of NASA

SiFive X280 delivers 100x increase in computational capability with leading power efficiency, fault tolerance, and compute flexibility to propel next-generation planetary and surface missions

NASA has chosen SiFive, Inc. to supply its core CPU for its upcoming High-Performance Spaceflight Computing (HPSC) processor. From planetary exploration to lunar and Mars surface missions, HPSC is anticipated to be used in almost all upcoming space missions.

HPSC will use four more SiFive RISC-V cores in addition to an 8-core SiFive IntelligenceTM X280 RISC-V vector core to provide 100x the computing power of current space computers. A number of mission components, including autonomous rovers, visual processing, space flight, guidance systems, communications, and other applications, will benefit from the dramatic improvement in computer performance.

Other government agencies are anticipated to benefit from the HPSC processor and X280 compute subsystem in a range of applications like as industrial automation, edge computing, ratification intelligence, and aerospace applications.

"As the leading RISC-V, U.S. based, semiconductor company we are very proud to be selected by the premier world space agency to power their most mission critical applications," said Jack Kang, SVP Business Development, SiFive. "The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem. We've always said that with SiFive the future has no limits, and we're excited to see the impact of our innovations extend well beyond our planet."

For more information on SiFive's market-leading RISC-V IP portfolio and how it is well-suited for Aerospace and Defense applications, please visit SiFive.com.

Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.

He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.

Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.

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