Frontgrade Gaisler and RISC-V's Space Journey
January 18, 2024
Story
The last time we spoke with Sandi Habinc, General Manager, and Jan Andersson, Director of Engineering at Frontgrade Gaisler, we were discussing the TRISAT-R CubeSat and Gaisler’s use of RISC-V’s open standard instruction set architecture within its space deployment.
What Has Happened Since?
Habinc and Andersson explained that within the last year, both NASA and the European Space Agency (ESA) added RISC-V to their core future. Both experts believe that we are reliving the 90s, so to say, when the 90s saw Europe push for the utilization of the SPARC architecture in space and then the U.S. followed suite by also adopting SPARC for U.S.-made space processors.
Now, Habinc says, “We are about to experience the same situation again for space, and this time it will probably be on a worldwide scale due to the adoption of RISC-V technology in Asia and other regions.” Leveraging the modern architecture of RISC-V, users can expect a wide range of applicable use scenarios.
Why?
RISC-V is a modern and scalable architecture designed to meet the demands of contemporary computing. Its design is modular and extensible, making it well-suited for evolving technological requirements. The modular nature allows for customization, enabling users to tailor the architecture to meet specific requirements. This is especially important in space applications where particular solutions are often necessary.
What is Gaisler's Position on SPARC Based Technology?
There is still a consistent need for LEON-based technology, and Gaisler plans to continue the support for its SPARC-based products in the foreseeable future. The LEON is a rad-hard, 32-bit SPARC processor developed for critical uses in space. Habinc clarifies, “The importance of legacy, heritage, and prior investments cannot be underestimated. And now, from what our Gaisler team is seeing in terms of customer needs and mission benefits, as well as abundance of software support, RISC-V is the future. “
The future of Frontgrade Gaisler is the GR765, an octa-core system-on-chip (SoC) which is state-of-the-art for space-grade processors in Europe. The GR765 implements a novel hybrid processor architecture, supporting both SPARC and RISC-V instructions. “This approach enables Gaisler customers to continue supporting their legacy SPARC software as they adopt the RISC-V platform,” Habinc says. “Depending on the type of application, customers can re-use their SPARC software or develop new applications that target RISC-V ISA opening software from other domains. We heeded the advice from smart people when moving the feature from a prototype chip into our GR765 product.”
Space Functions of RISC-V
In the realm of space applications, RISC-V serves diverse functions and plays a crucial role in various projects. Gaisler developed its RISC-V core as a general-purpose microprocessor for platform and instrument control applications, as well as a small controller processor to be embedded in FPGAs. The RISC-V architecture is expected to find future use in payload applications also, especially in multi-core processing solutions for tasks like image processing and artificial intelligence.
In microcontroller applications, typically only the IMA extensions are necessary. Introducing the C extension offers a method to minimize code size through an open standard and an established software toolchain. Another advantage of RISC-V technology lies in its physical memory protection (PMP), with Andersson noting that "the PMP functionality is more efficient and predictable compared to a full memory-management unit." As performance requirements increase, the hardware architecture extends to memory management and floating-point units, and the IMAFDBH extensions are implemented with the H extension providing hardware support for virtualization.
Frontgrade Gaisler chose to build an in-order dual pipeline as, “It represents a sweet-spot between implementation complexity and performance,” Habinc explained. Low complexity is a strength within space applications because it means that the processor pipeline can be understood and analyzed. In line with this, the processor offers a great deal of configurability so that users can turn off performance-enhancing features – such as buffers, caches, and predictors – to trade increased performance with complexity of software execution time analysis.
Obstacles
Andersson asserts that the complexity of software development for aerospace applications contributes to increased costs. The cost and complexity are due to the rigorous requirements on the development flow and end results. Frontgrade Gaisler is hearing from its customers that they believe software migration is the echelon of challenges when beginning to develop the RISC-V microarchitecture.
The future of RISC-V and space is wide open and launching into the next generation.
*Editor’s Notes:
NASA and the ESA collaborate on various missions, and both have chosen RISC-V technology as their go-to microprocessor.
The European Space Agency (ESA) and the Swedish National Space Agency (SNSA) supported the research and development process of both the GR765.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
