OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits, today announced its OneSpin 360 EC-FPGA now supports three Intel® field programmable gate array (FPGA) families, Stratix® 10, Arria® 10, and Cyclone® V.

The move to support FPGAs used in high-bandwidth applications meets increasing demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs from register transfer level (RTL) code to final netlist. OneSpin 360 EC-FPGA supports Cyclone V using Intel Quartus® Prime Standard Edition software for synthesis and place-and-route, and Stratix 10 and Arria 10 with Intel Quartus® Prime Pro Edition software for synthesis and place-and-route.

"We work closely with FPGA vendors including Intel to verify advanced optimizations in their leading-edge products, making EC-FPGA an essential part of successful design and verification," says Tobias Welp, OneSpin's engineering manager. "Adding Stratix 10, Arria 10 and Cyclone V to our extensive list of FPGA families is driven by users who rely on OneSpin 360 EC-FPGA to assure integrity for the most complex and demanding designs."

OneSpin's Support for High-Performance FPGAs

Cyclone V, Stratix 10 and Arria 10 are used in high-bandwidth applications that range from 5G communications, artificial intelligence, machine learning, data center acceleration and high-performance computing to radar processing, defense, automotive and medical. Applications like these require the latest synthesis technology to take advantage of architectural advances, such as specialized intellectual property (IP) blocks, and to meet timing and power specifications.

OneSpin 360 EC-FPGA ensures that advanced optimizations needed to meet aggressive power, performance and area goals do not change design functionality. Its sequential equivalence checking can determine whether these optimizations preserved the functional behavior of the design.

The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist, ensuring integrity through the logic and physical synthesis process.

EC-FPGA also detects unexpected functionality, unintentional logic inserted due to flow errors, and a variety of hardware Trojans and other malicious logic intentionally inserted. This assures trust in the final device.

In a separate news release today, OneSpin unveiled the RISC-V Verification App, the first App in the OneSpin RISC-V Integrity Verification Solution for safety- and security-critical applications.

Availability and Pricing

The latest version of OneSpin 360 EC-FPGA is shipping now, as is the RISC-V Verification App.

Pricing is available upon request.

OneSpin at DAC

EC-FPGA, the RISC-V Verification App and OneSpin's other certified IC integrity verification solutions will be featured at the 56th Design Automation Conference (DAC) in Booth #308 Monday-Wednesday, June 3-5, from 10 a.m. until 6 p.m. at the Las Vegas Convention Center.

DAC attendees can schedule demonstrations by going to http://www.onespin.com/dac.

OneSpin will host "Verified," the annual celebration of the verification ecosystem, at Topgolf Las Vegas at MGM Grand Monday, June 3, during DAC. A limited number of tickets is available from OneSpin or its co-hosts Agnisys, AMIQ EDA, Avery Design Systems, Blue Pearl Software, Breker Verification Systems, Concept Engineering, Dassault Systèmes, Imperas, Semifore and Verific Design Automation.