eSilicon
Suite 100
San Jose, CA 95002 [email protected]
(408) 217-7300
https://www.inphi.com/
ESD Alliance CEO Outlook 2019: eSilicon CEO Jack Harding to Participate - News
May 20, 2019eSilicon CEO Jack Harding will comment on the state of the application-specific integrated circuit (ASIC) market.
eSilicon Expands Technical Advisory Board - News
May 07, 2019Adds expertise in data science and big data analytics.
eSilicon Completes Tapeout of 7nm 400G Gearbox/Retimer Test ASIC - News
May 03, 2019The test ASIC includes x4 112 Gbps SerDes and x8 56 Gbps SerDes, which are integrated with media access control, forward error correction, and gearbox E-pak Ethernet IP from Precise-ITC.
eSilicon Signs Multi-Year Agreement with Google Cloud - Press Release
April 30, 2019Program will move company's IC design activities to Google Cloud Platform this year.
eSilicon to present at State of AI and ML - Spring 2019 - Press Release
April 02, 2019State of AI and ML-Spring 2019 conference to be held April 4 in Santa Clara, Calif.
Linley Spring Processor Conference 2019: eSilicon to demonstrate 7nm DSP SerDes over a 5-meter cable assembly and present on IP platforms - Press Release
April 02, 2019Registration for the event is open until 5:00 PM PDT on April 4.
DATE 2019: eSilicon to present two papers on advanced floor planning techniques with the Polytechnic University of Catalonia - Press Release
March 20, 2019Paper proposes a novel multi-level approach for macro placement of complex designs dominated by macro blocks