eSilicon
Suite 100
San Jose, CA 95002 [email protected]
(408) 217-7300
https://www.inphi.com/
Industrial
SC19: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Five-Meter Samtec Cable Assembly - Press Release
November 26, 2019eSilicon and Samtec co-developed system-level solutions that emulate next-generation data center architectures for typical 19-inch rack-mount applications
Processing
eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects - Product
October 07, 2019The PHY supports 2.5D applications such as silicon interposers and silicon bridges for system-on-chip (SoC) to chiplets and SoC partitioning.
Processing
ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies - Press Release
September 23, 2019eSilicon and Samtec will demonstrate eSilicon's 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for two challenging data center applications.
Processing
ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Five-Meter Samtec Cable Assemblies - Press Release
September 20, 2019eSilicon and Samtec will demonstrate eSilicon?s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for two challenging data center applications.
AI & Machine Learning
AI Hardware Summit 2019: Booth-to-Booth eSilicon 58G DSP-Based SerDes Demonstration Over a Five-Meter Samtec Copper Cable - Press Release
September 16, 2019eSilicon and Samtec partner to deliver a rare booth-to-booth long-reach SerDes demonstration at AI Hardware Summit 2019.
AI & Machine Learning
eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019 - Press Release
August 28, 2019New software maps high-level AI workloads to eSilicon's neuASIC modular AI ASIC IP platform.
Processing
eSilicon to Participate in Panel Discussion on Chiplet Design Experience at a Workshop presented by the Open Compute Project (OCP) - News
July 01, 2019Workshop will focus on new Open-Domain Specific Architectures (ODSA) sub-group