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Analog & Power

Embedded Executive: Develop an ASIC For Far Less Than $100K | Efabless - Podcast

February 26, 2025

Common knowledge says that if you want to create an ASIC, you’d better have at least $1M in your bank account. The folks at Efabless say that my common knowledge is inaccurate by a long shot. They claim to be able to get folks started for far less than $100k.

I needed to understand how this is possible, so I invited Michael Wishart, the CEO and co-founder of Efabless, to explain how it works on this week’s Embedded Executives podcast, with Kumar Gala and Maureen Helm, both Distinguished Engineers with Analog Devices.

Open Source

An Easier, Lower Cost Path to Customizable SoCs - Story

July 08, 2021

The electronics industry as we know it today is really built around three fundamental categories of products (we might call them the three "S's"):  software, semiconductors, and systems. Innovation happens in each of the three categories which spurs further progress, creating a "virtuous cycle" driving the whole industry forward. Innovation in software has always had the lowest barrier to entry from a financial perspective - literally anyone with decent coding skills and a computer can start with very little money needed for anything else.  Creating system-level hardware has been only slightly more financially challenging.  Just about anyone can get some relatively low-cost PCB layout software, design a board, and then gather a small amount of money to buy some chips and have their board or boards fabricated. 

Processing

Embedded Executive: Jeff DiCorpo, SVP Business Development, efabless - Podcast

July 07, 2021

Develop an ASIC for less than $10,000? I didn’t believe it either. But according to Jeff DiCorpo, a Senior VP at efabless, not only is it possible, but people are doing it with his company’s tools. Learn how to generate your own design on this week’s Embedded Executives podcast.

Open Source

X-FAB, Efabless Release First Silicon of Raven RISC-V SoC - News

June 13, 2019

A mixed-signal SoC, nearly 75 percent of Raven?s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz.