Embedded Computing Design

Tom Jose

ASIC DESIGN ENGINEER

ELC Labs

Hardware Design Engineer, interested in Logic Design, Interface Design, Design Debug and Hardware/Software Co-Processing. Skilled in micro-architecture development, RTL-coding, Synthesis, Verification and Lab Validation. Holds Masters Degree in Electrical Engineering(VLSI Design) from University of Cincinnati(USA)[2014-15]. Bachelor Degree from College Of Engineering Trivandrum(India)[2005-09].

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Security

Accurate Measurement of Latency and Throughput of Time Sensitive Networks - Story

February 01, 2019
Tom Jose

This article is on the IEEE standard IEEE802.1Q Time Sensitive Networking (TSN).

Articles 1 - 1