If you’re following the trends in flash storage devices these days, you’ve inevitably seen the amazing advances in storage capacity at constantly reducing price points. But when you look at what’s behind these advances, you’ll notice the higher capacity and lower cost comes with a penalty to reliability.

Industrial-grade flash storage, based on SLC NAND, is more costly, but also the most reliable NAND flash solution available to embedded systems designers. CompactFlash cards are available as low as 128 Mbytes, which allow great reliability for a low unit cost. Two key items driving costs down and capacities up are an increased NAND bits per cell and finer trace width geometries in the silicon.

Let’s touch on the NAND bits per cell. When NAND was originally invented, there were only two states inside a cell. They were recognized as either a high or a low. This is known as single-level-cell (SLC) NAND.

As time went on, advances in silicon architecture allowed two bits per cell to be stored. Called multi-level cell (MLC), it effectively stored twice the data in the same space. It required the ability to store four distinct states in the NAND cell representing a 00, 01, 10, and 11.

The latest craze in NAND flash, which started on consumer flash cards and is slowly migrating to consumer devices, is the 3-bit per cell NAND architecture. To store the 3 bits, a tri-level cell (TLC) NAND must be able to store and retrieve eight different states in the same area that the original SLC NAND stores two.

So what does this mean for reliability of flash cards and embedded systems using the lower cost MLC and TLC memory? It means less reliability. The current MLC NAND has about 3,000 erase cycles per block and TLC NAND can have as few as 300. This compares to SLC at 50,000 to 70,000 erase cycles per block.

The second NAND trend driving capacity higher and cost lower is the NAND silicon’s trace width. As you shrink the widths to finer and finer geometries, you can fit more memory on a given piece of silicon.

Today’s MLC NAND is being driven quickly from the 19/20-nm trace width to 15/16 nm, while SLC continues to be available in the 43-nm width. Finer trace width introduces a couple of factors that can be detrimental to reliability, program, and read disturb.

Program disturb is caused when a NAND cell is programmed. Since higher voltage levels are needed to program a cell, the state of adjacent NAND cells may be affected unexpectedly. MLC and TLC NAND are more sensitive to program disturb due to their smaller voltage margins per state.

Read disturb isn’t as severe an issue as program disturb, but it’s becoming an issue as trace widths continue to shrink. This phenomenon occurs when cells adjacent to those being read are affected by stray charges coupled to the floating gates of the unselected cells.

In summary, if reliability of a long life embedded design is a must, industrial-grade flash storage should be a priority for your system.

Steve Larrivee is Vice President, Sales and Marketing at Cactus Technologies Limited. He has over 30 years of experience in the data storage market, including 10 with SanDisk and 5 with Seagate Technology.