The electronics industry is moving from being hardware-defined to being system-defined, while electronic products become increasingly application-driven. As a result, product differentiation has shifted to system (software-based) content, while hardware platforms and their development processes become more and more commoditized. Seizing new opportunities in this emerging segment requires expanding upon the foundations of the electronics industry. The needs of system developers must be addressed, and the responses to those needs must be integrated into a single solution.

The potential risks involved with schedule delays and product quality have become vast. Time-to-market pressures and the trend toward software-defined product functionality make the traditional sequential process, where System-on-Chip (SoC) development is followed by board and device development and then by software development, obsolete. Meeting functionality, power, and performance as system bring-up occurs has become the most challenging task. System bring-up consumes one-third to one-half of the overall development cycle for many OEM companies, with product quality and predictability becoming the second and third priorities. System bring-up is a top OEM executive concern, as it can make or break the profitability of their products.

If you have participated in the debate over system realization, your questions likely go something like this:

• What is the best approach to system-level validation?
• Should we invest in the promise of faster virtual platforms while dealing with their inherent timing inaccuracy?
• Is the FPGA-based prototyping approach – with its low cost but long bring-up time – enough to get the job done?
• Should we rely solely on system emulation or simulation acceleration?
• How can these technologies be leveraged to enable collaboration with our IP suppliers and customers?

In the past 15 years, I have participated in dozens of panels and roundtables where such questions were raised. The answers largely depended on the responsibility of the specific person in charge or the offerings of his or her company, with some people changing their answers when they changed companies. Over the years, we (at Cadence) realized that the specific product being offered is not as important. What is important is the value the customer gets and the resources, time, and money they need to spend. We have also realized no one product or platform can solve all system verification and validation problems. A combination of multiple platforms is required.

Is the biggest challenge to successfully completing your next-generation design avoiding silicon re-spins, getting the ever-increasing amount of software done on time, or finding ways to validate the interaction between hardware and software?

Many verification teams use an ad hoc portfolio of technologies and disjointed environments and platforms to the point where they can’t get the job done. To keep pace with the demands of advanced system development, the traditional approach simply isn’t productive enough. Verification throughput is failing to satisfy the requirements of today’s increasingly complex designs. Based on recent discussions with verification teams of large and complex systems, finishing complex verification tasks using Register Transfer Language (RTL) simulation no longer works. What’s needed is a high-performance environment suitable for hardware verification, low-level firmware, and software development within a system context throughout the design process.

The big picture solution must deliver a unifying flow that offers users a familiar environment able to maximize and expand the simulation capabilities for both subsystem and system-level simulation. The environment and the performance need to be appealing and attractive for system, software, and hardware verification teams. Cadence envisions a flow that combines open, connected, scalable, and best-in-class hardware/software platforms, including hardware-assisted verification and software-based tools. The integrated flow will need to break new ground in delivering scalable usability for both design-team and enterprise-class customers, connecting design and verification flows throughout multiple levels of abstraction, offering high performance and a flexible modeling environment. Imagine what you can do with an integrated flow for system realization.

Business pain points

Time to market is the number one challenge of system developers and system companies. Companies (especially in the consumer market) are under pressure to meet their market window and to reduce their overall design cycle from 12 to 6 months. These firms need to be able to communicate and interact efficiently with their suppliers and partners with predictable schedules. CEOs want to embark on revolutionary paths to transform their organizations from chip or IC makers to system companies.

During this transformation, company leaders need to integrate their hardware and software teams into one. An approach of developing standard products that serve and win specific applications in the market will give way to hitting the market at the right time while meeting the specifications. At the same time these forward-looking companies will be collaborating with partners who are generating content (Facebook, Google, Netflix, and similar organizations or operators such as AT&T, Comcast, and Verizon). As a result, electronics industry players are at high risk to miss their market window unless they will change the way they develop systems. Figure 1 shows the potential revenue loss risk as a result of missing market windows in slow, medium, and fast market segments. A six-month delay could cause an average loss of $50 million.

Technical pain points

As system design complexity (think multicore, multithreading, multitasking, and rapidly increasing software content) grows, it becomes more challenging to meet application-driven requirements. A key challenge is shifting from chip tape-out to time to market. System hardware/software bring-up and integration are key bottlenecks. Current offerings meant to loosen these bottlenecks are on proprietary instrumentation, employ nonconfigurable models, and aren’t easily ready to plug into third-party tools. What’s more, these products are fragmented, with disconnected point tools that leave the burden of integration and migration from one development phase to another to the users. And these offerings limit themselves to solving just a single level of abstraction.

The customers’ ideal is a single platform that can address all their needs. Unfortunately, no single hardware/software development platform can address all design phases. Therefore, a single solution/flow based on a combination of multiple platforms is required. Each platform focuses on each phase of the flow with different optimized characteristics.

For example, early in the design users require a platform that can run their software on top of an abstract model of the hardware. Later on in the process they need to run their software on top of an accurate representation of the hardware. Customers spend months and many dollars migrating manually across platforms. They need a continuum set of open and connected platforms. The open platforms selected should be standard-based and have third-party support. Connected platforms should have integrated offerings, methodology, and flow to allow users to migrate automatically from one platform to another. Successful platforms will support the hardware/software verification and integration process throughout the flow with scalable performance and capacity to support multiple levels of abstraction.

A comprehensive set of open, connected, and scalable platforms for system realization

Cadence addresses the technical challenges mentioned earlier through the development and delivery of a comprehensive set of hardware/software platforms called System Development Suite. The suite is open, connected, and scalable with a strong ecosystem partnership, services, and an integrated methodology. Building on its industry-leading offerings in advanced verification and acceleration/emulation, this continuum creates in the market an approach to address the key system development challenges. As seen in Figure 2, this approach includes four hardware/software platforms with performance trade-offs. Although all these platforms enable validation and integration of hardware and software, some platforms focus more on hardware validation and verification, while others target higher performance for software developers. Although all the platforms can participate throughout the whole design process, each platform is optimized to serve users at different phases of system development.

Each platform is uniquely connected to the next one in order to speed up the bring-up time of the hardware/software environment as users migrate from one development phase to another.

Virtual System Platform

The Virtual System Platform’s tools for system developers help them to create and analyze virtual platforms/prototyping. Software developers gain a platform to run their software on top of abstracted models for early software development and software distribution. It is open (standard-based) and delivers scalable performance and superior hardware/software debug capabilities. It connects to the Incisive Verification Platform through a unified simulator and common verification IP.

Incisive Verification Platform (with Incisive Enterprise Simulator)

This platform’s advanced verification tools address block/chip-level verification based on an open methodology (UVM) with a rich portfolio of optimized verification IP that can be extended to other platforms. It helps verification engineers bring up the firmware and provides hardware/software metric-driven verification capabilities that also work with the Virtual System Platform and the Verification Computing Platform.

Verification Computing Platform (Palladium XP)

Users will find cycle-accurate system validation (emulation) and acceleration capabilities with scalable capacity and performance available with this platform, which includes hardware/software debug capabilities. This platform is open, provides fast bring-up and turnaround time, and delivers low-power verification and analysis as well as metric-driven verification capabilities. It is connected to the Incisive Verification Platform through hot swap, common debug, runtime, compile, and verification IP.

Rapid Prototyping Platform

The FPGA-based Rapid Prototyping Platform serves as a cycle-accurate software development platform with the ability to connect into real-world interfaces in order to run exhaustive regressions. It allows distribution of multiple, affordable prototypes to software developers. It is open, supports standard-based ASIC flows, and provides scalable bring-up and debug with a high level of accuracy. Together with the Verification Computing Platform, the combined solution provides common compile flow, SpeedBridge adapters, and powerful debug.

Summary

• The electronics and semiconductor industries have undergone a major shift in the past decade, where software has eclipsed hardware as the main driver of system development cost, schedule, and risk.
• System integration time is the main challenge of system developers and system companies.
• Current offerings in the market are closed, fragmented, and limited.
• To address system development cost, schedule, and risk challenges a comprehensive set of open, connected, and scalable hardware/software platforms that accelerate the migration from one platform to another is required.

Ran Avinun is the product marketing group director for System Design and Verification at Cadence Design Systems. He has served Cadence in the past 12 years in senior marketing management positions with a focus on hardware-assisted verification and the ESL market segments. He has 23 years of experience in the EDA and semiconductor industries. Ran also worked at Quickturn, inventor of In-Circuit Emulation (later acquired by Cadence), and Chip Express (a fast ASIC prototype manufacturer) in engineering and marketing roles. He began his career as an application engineer with Daisy Systems. Ran holds a BSE and MSE in Electrical Engineering from the Technion and Tel Aviv University in Israel and an MBA from the University of Phoenix in California.

Cadence Design Systems [email protected] www.cadence.com