Synopsys Announces Newly Powerful UCIe Multi-Die Designs in 40 Gbps Spec
September 11, 2024
Story
Synopsys has announced a brand new UCIe IP solution operating at up to 40 Gbps per pin and the company says it’s targeted directly at the computing needs of data centers layered with ever-more sophisticated AI applications.
Of course, the new IP is based on the UCIe interconnect, and Synopsys asserts that this was critical to the development of the high-bandwidth, low-latency die-to-die connectivity in this kind of multi-die package. It enables more data to travel efficiently across heterogeneous and homogeneous dies, or chiplets, which is what’s required for modern and future AI data center systems.
“The writing was on the wall that multi-die is here, and UCIe is enabling that rapid adoption we’re seeing,” said Michael Posner, VP, IP product management, Synopsys. “We want to stay at least one generation ahead of development.”
According to the release, this 40G UCIe IP supports both organic substrate and high-density, advanced packaging technologies to give designers the flexibility to explore custom packaging options.
“Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications,” said Jongwoo Lee, VP, System LSI IP Development Team, Samsung Electronics. “Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow’s high-performance data centers."
“Launching the industry’s first complete 40G UCIe IP solution underscores Synopsys’ continued investment in advancing semiconductor innovation,” added Posner. “Our active contribution to the UCIe consortium has enabled us to deliver a robust UCIe solution that helps our customers successfully develop and optimize their multi-die designs for high-performance AI computing systems.”
Capabilities of the new solution include:
- Easier IP Integration: Single reference clock feature to simplify the clocking architecture and optimize power. The IP speeds up die-to-die link initialization without the need to load the firmware.
- Silicon Health Monitoring: To ensure reliability at the die, die-to-die, and multi-die package levels, the company offers test and silicon lifecycle management (SLM) features, including monitoring, test, and repair IP and integrated signal integrity monitors for diagnosis and analysis from in-design to in-field.
- Interoperability: For on-chip interconnect needs of the latest CPUs and GPUs, the product supports popular on-chip interconnect fabrics including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. The IP is compliant with the UCIe 1.1 and 2.0 standards.
- Pre-Verified Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, is used in the pre-verified design reference flow that includes all the required design collateral such as automated routing flow, interposer studies, and signal integrity analysis.
Availability & Additional Resources
The Synopsys 40G UCIe IP will be available in late 2024 for multiple foundries and processes.
- Web: Synopsys UCIe IP Solution
- Blog: Synopsys Introduces Industry’s First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
- Blog: UCIe 2.0 - Setting the Tone for Chiplet Interoperability
Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.
