The RISC-V Foundation will be at embedded world from February 26-28 in Hall 3A, Booth No. 3A-536 in Nürnberg, Germany.

The company will host live demonstrations from RISC-V Foundation co-exhibitors including Andes Technology, CloudBEAR, GreenWaves Technologies, Imperas Software, SiFive, Syntacore and UltraSoC.

Throughout the show, the booth will feature speaking sessions including:

Session 5.1: RISC-V I Overview (Feb. 26)

• RISC-V: Practical Industry Approach to Getting Started with This Technology
  • When: 9:30 – 10 CET
  • Who: Robert Oshana, NXP Semiconductors
• How to Benefit from RISC-V Based Linux for Embedded Industrial Applications
  • When: 10:00 – 10:30 CET
  • Who: Krishnakumar R, Microchip Technology
• The Soul of a New SoC: Hands-on Experience with Embedding a RISC-V Core
  • When: 10:30 – 11 CET
  • Who: Onno Martens, Trinamic Motion Control Gmbh & Co. KG
• Methodology for Implementation of Custom Instructions in the RISC-V Architecture
  • When: 11:30 – Noon CET
  • Who: Larry Lapides, Imperas Software
• Compliance Methodology and Initial Results for RISC-V ISA Implementations
  • When: Noon – 12:30 CET
  • Who: Lee Moore, Imperas Software

Session 5.2: RISC-V II Security (Feb. 26)

• Maintaining Security in a Heterogeneous and Changing World
  • When: 14:30 – 15:00 CET
  • Who: Jon Geater, Jitsuin; Cesare Garlati, prpl Foundation and Hex Five Security

• A New Zero-Trust Model for Securing Embedded Systems
  • When: 15:00 – 15:30 CET
  • Who: Chris Conlon, wolfSSL; Cesare Garlati, prpl Foundation and Hex Five Security

Session 5.3: RISC-V III System (Feb. 26)

• User Mode Interrupts: a Must for Securing Embedded Systems
  • When: 16:00 – 16:30 CET
  • Who: Prof. Sandro Pinto, Universidade do Minho; Cesare Garlati, prpl Foundation and Hex Five Security
• Embracing a System Level Approach: Combining Arm & RISC-V in Heterogeneous Designs
  • When: 16:30 – 17:00 CET
  • Who: Gajinder Panesar, UltraSoC
• RISC-V: High Performance Embedded SweRV Core Microarchitecture, Performance and Implementation Challenges
  • When: 17:00 – 17:30 CET
  • Who: Dr. Zvonimir Bandic, Western Digital

Class 5.2: RISC-V Workshop (Feb. 27)

• How to Build a RISC-V Embedded System In Just 30 Minutes
  • When: 9:30 – 10:30 CET
  • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Drew Barbier, SiFive
• How to Secure a RISC-V Embedded System In Just 30 Minutes
  • When: 10:30 – Noon CET
  • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Don Barnetson, Hex Five Security
• Trusted Execution Environments: A System Design Perspective
  • When: Noon – 12:30 CET
  • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Boran Car, Hex Five Security

Session 6.3: Software Engineering II Design & Modeling (Feb. 27)

• Design Cycle Acceleration for Hardware/Software Co-Design with Renode
  • When: Noon – 12:30 CET
  • Who: Steve Milburn, Dover Microsystems and Michael Gielda, Antmicro

Expert Panel (Feb. 27)

• Opportunities and Risks in Open Source Processors
  • When: Noon – 13:00 CET
  • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Markus Levy, NXP Semiconductors; Ted Marena, Western Digital; Tim Whitfield, Arm

The RISC-V Foundation also plans to host a scavenger hunt for attendees to visit different booths within the RISC-V ecosystem in search for various objects for a chance to win a prize.  

For more information, please visit: www.risc-v.org.