Microchip Technology Inc.’s  SMC 1000 8x25G helps CPUs and other compute-centric SoCs leverage four times the memory channels of parallel attached DDR4 DRAM within the same package footprint, providing higher memory bandwidth and media independence.

The SMC 1000 8x25G interacts with the CPU via 8-bit Open Memory Interface (OMI)-compliant 25 Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface, resulting in reduced host CPU or SoC pins per DDR4 memory channel, providing more memory channels and bandwidth.

It includes a low latency design that offers less than four ns incremental latency over a traditional integrated DDR controller with LRDIMM, producing OMI-based DDIMM products with equal bandwidth and latency performance to LRDIMM products of its kind.

“Microchip is excited to introduce the industry’s first serial memory controller device to the market,” said VP of Microchip’s Data Center Solutions business unit, Pete Hazen. “New memory interface technologies such as OMI enable a broad range of SoC applications to support the increasing memory requirements of high-performance data center applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data center.”  

The SMC 1000 8x25G is now available for sampling. To order samples, visit: https://www.microchip.com/smartmemory.

Learn more at www.microchip.com.