Pentek introduced the Model 54851, a member of the Jade family of high-performance 3U VPX boards, based on the Xilinx Kintex Ultrascale FPGA. Features include two 500 MHz 12-bit A/Ds with two programmable multiband digital downconverters (DDCs), and one digital upconverter (DUC) with two 800 MHz 16-bit D/As.

“Recent enhancements to OpenVPX have greatly improved I/O capabilities,” said Robert Sgandurra, director of Product Management. “These enhancements play well into Pentek’s modular approach to product design by offering optical and RF options for high-performance I/O that perfectly match our product capabilities.”

The Model 54851 takes advantage of these VPX I/O options for RF and optical interconnects through the VPX backplane:

            • Option -110: Optical connections based on VITA 66.5 (draft), containing blind-mate MT optical connectors with fixed contacts on the plug-in module and floating displacement on the backplane.

            • Option -111: RF connections based on ANSI/VITA 67.2, containing multi-position blind-mate analog connectors with SMPM contacts.

            • Option -112: RF connections based on ANSI/VITA 67.3 type C, containing multi-position blind mate analog connectors with SMPM contacts, spring-loaded on the backplane allowing more movement and larger diameter cables for better performance.

The Model 54851 can be populated with a range of Kintex UltraScale FPGAs to match specific requirements of the processing task, spanning from the entry-level KU035 (with 1,700 DSP slices) to the high-performance KU115 (with 5,520 DSP slices). The KU115 suits demanding modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, a lower-cost FPGA can be installed.

The Model 54851 also includes a complete multi-board clock and sync engine and a large DDR4 memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 54851 includes optional high-bandwidth connections to the Kintex UltraScale FPGA for custom digital I/O.

The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50 percent with equally impressive reductions in cost, power dissipation, and weight. Its PCI Gen.3 interface allows access to control and status registers for controlling algorithms, state machines and data flow across the LVDS I/O front panel and carrier board interfaces. A 5 GB bank of DDR4 SDRAM is available for additional functions. The factory-installed DMA controller can sustain 6.4 GB/s data transfers across PCIe.

Pentek’s Navigator Design Suite was designed to work with the Jade architecture and Xilinx’s Vivado Design Suite to provide a solution to IP and control software creation and compatibility. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. The Navigator BSP is available for Windows and Linux operating systems.

Learn more at www.pentek.com.