Codasip announced three new 64-bit RISC-V application processor cores: the A70XP provides support for RISC-V P extensions, and the A70X MP and A70XP MP enable the creation of symmetric multi-processor (SMP) systems.

The RISC-V P extension consists of 331 instructions which can be divided into groups. The A70XP includes a SIMD unit which executes P extension instructions with single-cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. Applications for this core include audio encoding/decoding, sensor fusion, computer vision, and edge AI/ML applications.

The A70X-MP and A70XP-MP cores add multi-core features to the Codasip application processor family, supporting clusters of up to four cores in an SMP configuration. Codasip provides configurable L1 and L2 caches with a scalable microarchitecture. All Codasip application processors, the A70X, A70XP, A70X-MP, and A70XP-MP, use an AXI external interface and support Linux.

Codasip's new family of Application RISC-V processors (names beginning with "A") is based on the same microarchitecture as the A70X (Codasip Bk7). All the Application cores are 64-bit and feature a Floating Point Unit and Atomic instructions. They also support Machine, Supervisor, & User privilege modes and have a Memory Management Unit, therefore they are able to run Linux. Like other Codasip RISC-V cores, they are developed using Codasip Studio allowing them to be customized to meet domain-specific requirements.

The A70X core is available today and the other three cores will be available in the first quarter of 2021.

For more information, visit: www.codasip.com or www.riscv.org