Intel and Codasip Collaborate to Bring Project-Based RISC-V Assignments to Undergraduate and Graduate Courses
December 02, 2022
News
Munich, Germany – The Codasip University Program has joined Intel Pathfiner for RISC-V in a collaboration to bring Codasip RISC-V IP cores, the Codasip Studio development environment, and Intel's FPGA platforms to undergraduate and graduate courses. Codasip's University Program is currently working with a number of universities, in light of the expansion of Intel’s Pathfinder ecosystem, to provide students with access to Codasip Studio and project-based RISC-V assignments.
Beginning fall 2023, the Codasip University Program will utilize Intel Pathfinder for RISC-V FPGA development boards for graduate SoC and undergraduate High-Level Synthesis (HLS) & Verilog curriculum assignments. Intel® Pathfinder for RISC-V will allow students to take advantage of RISC-V and peripheral IP for Intel’s FPGA boards, giving them the ability to gain knowledge about configurations and combinations of IP.
“The addition of Intel’s FPGA platforms into Codasip’s computer architecture project-based assignments will further boost our three University Program Pillars; preparing the next generation of researchers, training the next generation of engineers, and developing solutions to solve tomorrow’s technological challenges,” said Keith Graham, Vice President of University and Customer Experience Program, at Codasip.
For more information, visit: www.codasip.com and www.riscv.org
To register for the Codasip University Program, visit: https://codasip.com/university-program/
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Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
