Solid Sands' SuperTest to Help SiFive Advance RISC-V
January 31, 2022
News
SiFive is currently building a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development.
These new developments include compiler algorithms, build system integration, and new Verilog RTL generation techniques. SiFive needed a compiler test and verification tool, not only to verify the functionality of its existing compiler offering, but also to help develop its new IDE infrastructure. The tool SiFive chose was Solid Sands' SuperTest.
SiFive currently uses SuperTest for verification and testing of the GCC and LLVM compilers and libraries it supplies with its IDE, as well as for regression and release testing. Over the two years the company has been using it, SuperTest has helped to identify several previously unknown code generation errors in both compiler systems.
SiFive is also the provider of RISC-V IP and one of the contributors at RISC-V International, the non-profit organization that supports the free and open RISC-V instruction set architecture and extensions. The attractions of RISC-V are two-fold. Firstly, the ISA is license free, removing the cost barrier for adoption by commercial, research, or academic users. Secondly, the architecture is modular, extensible, and customizable, allowing the addition of application-specific instructions and hardware acceleration features at the architecture level, while also leveraging the benefits of industry-wide development of ratified standards for extensions.
For example, SiFive has recently introduced its SiFive Intelligence X280, which extends RISC-V with SiFive Intelligence Extensions that integrate dedicated AI acceleration technology and extended data type support into the RISC-V instruction set architecture. With comprehensive support for TensorFlow Lite, the result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of machine learning models.
Because adding application-specific instructions has implications for the compiler and potentially also the libraries, similar enhanced RISC-V architecture developers may want to take advantage of SuperTest’s comprehensive verification capabilities, such as its CGTrainer code generator trainer, which provides a systematic way of testing a modified compiler’s back-end. In such situations, SuperTest also provides a way of checking that the basic functionality of the compiler − its correct implementation of the C or C++ language specification − is not broken by the addition of these new instructions.
For more information, visit: https://solidsands.com/ and https://www.sifive.com/
Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.
She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.
Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
