Undervolting, i.e., supply voltage underscaling below the nominal level, is an effective technique to reduce the underlying hardware's total power consumption since it decreases the dynamic power quadratically and the static power linearly. Usually, chip manufacturers add a large voltage guardband below the nominal voltage level to ensure the correct functionality under the worst-case process and environmental conditions. However, for many real-world applications, this voltage guardband is unnecessary and conservative; in turn, it adds a hefty power consumption penalty. Hence, eliminating this voltage guardband can deliver significant power-saving without any performance or reliability overhead. However, further Undervolting below the guardband region incurs overhead, either for the performance when the operating frequency simultaneously underscales or for the reliability when the underlying hardware is operating at the maximum frequency.

In the literature, Undervolting has been studied for computing devices like CPUs and GPUs as well as for memory storage like DRAMs. We extended and thoroughly investigated the Undervolting technique (including the voltage guardband analysis for real FPGA chips, fault characterization and mitigation below the guardband, workload characterization, etc.) for modern Field Programmable Gate Arrays (FPGAs). We have demonstrated the significant potential of this technique for FPGAs to deliver more than 10x power-saving gain, through which the power-efficiency gap between FPGA- and equivalent Application Specific Integrated Circuit (ASIC)-based accelerators can be effectively bridged. The results have obtained significant attention in academia and are published in top-tier venues like MICRO'2018 [1] and DSN'2020 [2].

We are aiming to transfer our FPGA Undervolting technique, developed in the LEGaTO project, to industry, especially for embedded Deep Learning (DL) applications. DL applications are intensively power-hungry due to their naturally high demand for massive data movement and computational power. This issue is even more critical for embedded scenarios like IoT and mobile devices due to the limited hardware resources. Hence, we believe that our FPGA Undervolting technique can significantly improve such applications' power-efficiency and in turn, facilitate their deployment in real-world industrial environments. In general, lowering energy consumption is obviously a good thing from an environmental and economical point of view. This is even more relevant to applications that carry their own energy source, e.g. drones and electric cars. Battery retention time is a very important feature of many products. Moreover, there are many applications where the energy consumption of today’s DL system dampens the product innovations, e.g. in smart homes. If we are to realize the intelligent future depicted in the media today, the energy consumption of the intelligent systems needs to be really low. In this line, energy efficiency is extremely important to several domains like the automotive and telecom industry.

By exploiting the Undervolting technology, we expect to reach close to 10X energy improvement on the same FPGA hardware. We expect to be able to attract several customers due to this project and increase the market share in the IoT domain, where low energy usage is critical, which will lead to several new job opportunities to further extend our technology stack. The technology transfer of our FPGA Undervolting technique to the industry is supported by Tetramax under the LV-EmbeDL project and in collaboration with EmbeDL AB. The LV-EmbeDL project received the "Certificated of Excellence" label from I4MS-SAE (promoted by the European Commission).

[1] B. Salami, et al., "Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-chip Memories", in MICRO, 2018.

[2] B. Salami, et al., "An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration," in DSN, 2020.

About the Author

Behzad Salami is a researcher at BSC and received a Ph.D. degree (Hons.) in Computer Architecture from UPC. He is the PI of a technology transfer project granted by Tetramax, i.e., LV-EmbeDL. His research interest is low-power and fault-resilient hardware accelerators.