Esperanto Technologies to develop energy-efficient AI chips on RISC-V architecture
November 28, 2017
Mountain View, CA. In a presentation at the 7th RISC-V Workshop, Esperanto Technologies announced that it plans to develop energy-efficient computing solutions for artificial intelligence (AI) and machine learning based on the open standard RISC-V Instruction Set Architecture (ISA). The company’s first RISC-V AI system on chips (SoCs) will leverage 16 ET-Maxion 64-bit RISC-V cores, 4,096 energy-efficient ET-Minion RISC-V cores (each with a vector floating point unit), and be designed on 7 nm CMOS process technology.
“By designing in leading-edge 7 nm CMOS and with the simplicity of the RISC-V architecture, we can fit over 4,000 full 64-bit cores each with vector accelerators on a single chip,” Dave Ditzel, President and CEO of Esperanto Technologies said during a presentation entitled Industrial-Strength, High-Performance RISC-V Processors for Energy-Efficient Computing. “By basing our chip on RISC-V we can take advantage of the growing software base of operating systems, compilers, and applications. RISC-V is so simple and extensible that we can deliver world-class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability.”
Esperanto Technologies also plans to license its ET-Maxion and ET-Minion cores to help proliferate the RISC-V architecture.
For more information on Esperanto Technologies, visit www.esperanto.ai. For more on the RISC-V Foundation or 7th RISC-V Workshop, go to https://riscv.org/.
