Chad Cox

November 19, 2024

San Jose, California. Point2 Technology introduced the Point2 P1B12,1 its innovative Smart Retimer system-on-chip (SoC) for AEC applications in hyperscale AI/ML datacenters. It incorporates eight-unidirectional SerDes channels with smart Clock Data Recovery (CDR)/Retimer operations that support 112G PAM4 and 56G NRZ data rates. The Point2 P1B121 is designed for low-power and low-latency operations in 800 gigabit (800G) and 1.6 Terabit (1.6T) Active Electrical Cables (AECs). At 3 nanoseconds (3ns), the P1B121 chip latency is 20X lower than standard DSP-based PAM4 Retimers.


 

Chad Cox

November 18, 2024

As the need for faster, more efficient data processing increases, Field Programmable Gate Arrays (FPGAs) are a fundamental technology bridging the gap between traditional hardware accelerators and cutting-edge applications like Artificial Intelligence (AI). They are becoming a critical building block for innovations from edge computing to cloud infrastructure.