aicas GmbH and SiFive are collaborating to integrate the RISC-V CPU architecture and JamaicaVM Java-based software management.

AWS, SiFive, and aicas during embedded world 2021 will deliver a virtual demonstration of AWS IoT Greengrass 2.0 running on a SiFive RISC-V unmatched board.

Is the RISC-V standard bearer ditching its heritage to become a design mercenary by using Arm? Or is this a longer-term play to help get RISC-V technology into SoCs so it can grow from there?

Different vendors are doing different things to cope with the COVID-19 pandemic. Many of them are doing their part to help get us through this awful time. One of those is SiFive.

The new working groups will build from progress in the SIL2LinuxMP and Real-Time Linux projects to help bridge gaps between the safety standards and Linux development ecosystems.

As SEGGER strengthens its position within the RISC-V instruction set architecture, the company announced its J-Link probes deliver support for the new SiFive Insight debug/trace solution.

The Learn Inventor kit is designed around one of the first commercially available RISC-V SoCs, the SiFive FE310-G003. That chip is built around SiFive?s E31 Core Complex.