As SoCs and memory provide more capabilities, they also become more complex. And the more complex they become, the more difficult the verification process is for chip designers. They need increasingly advanced simulation technology that ensures each circuit meets the chip’s specifications and requirements.

Recent changes in the semiconductor industry are creating new challenges for verification of memories and SoCs. Verifying these complex designs is complicated because of evolving newer architectures, increasing design sizes due to advanced-node processes, and the exponential increase in layout parasitics.

SAN JOSE, Calif., February 24, 2021—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has completed the acquisition of NUMECA International.

With native bi-directional traceability and in-tool access to native CAD data structures, engineering teams can easily share high-fidelity design changes and other information that help reduce develo

Cadence recently announced its Tensilica ConnX B20 DSP IP that provides a fast, power-efficient solution for the automotive and 5G communications markets.

FPGA-based prototyping has been key starting the software-development process as early as possible, but growing complexities and shrinking time-to-market are making prototype bring-up more difficult.

I had a brief encounter with Cadence’s Krishna Balachandran, who is responsible for low-power products. As you can see in the video, I handled the toughest part of the interview — pronouncing Krishna’