Munich, Germany – The Codasip University Program has joined Intel Pathfiner for RISC-V in a collaboration to bring Codasip RISC-V IP cores, the Codasip Studio development environment, and Intel's FPGA platforms to undergraduate and graduate courses. Codasip's University Program is currently working with a number of universities, in light of the expansion of Intel’s Pathfinder ecosystem, to provide students with access to Codasip Studio and project-based RISC-V assignments.

Concurrent Technologies released its Intel® Core™ i7 processor powered Helios, an ITAR-free Commercial Off The Shelf (COTS) rugged industrial computing vision system with optimal Size, Weight, Power and Cost (SWaP-C) envelope able to withstand the harshest edge environments. Included is an Nvidia® graphics module with adequate I/O and storage plasticity for command-and-control display, degrade vision enhancement, and 360° vehicle navigation.

SAN JOSE, CALIFORNIA. Intel recently announced its 13th Gen Intel® Core™ processor family with six unlocked desktop processors that feature up to 24 cores, 32 threads, and clock speeds of up to 5.8 GHz. The 13th Gen Intel Core desktop family will include 22 processors and over 125 partner system designs that developers can couple with the newest supportt for DDR5 memory support and existing support for DDR4 memory support to create custom setups.

The IVX-1000 from Vecow leverages power from a 12th generation Intel Core i9, i7, i5, and i3 processor. The easy to deploy system is ideal for railway applications as it ensures applications run effectively, dependably, and safely thanks to the 16V to 160V wide power input, 4kV DC isolation, up to 500V Surge Protection, smart battery, ICY Dock Tray, and a full complement of I/O interfaces, including M12 GigE LAN, 4 USB, 4 COM, and wireless connectivity.

NEXCOM created the FTA 5180 to accommodate the growing demand of wireless, adaptable, and space-saving edge appliances.

MIPS is working with Intel to accelerate innovation in open computing

RISC-V is an open-source instruction set architecture (ISA) built on the principles of the reduced instruction set computer (RISC), which was first created at the University of California, Berkley. It enables open modular building blocks necessary for contemporary computing.