Silicon Labs 5G-Ready Jitter Attenuators Future Proofed for 112G Serdes
June 20, 2019
Product
The 100 Hz to 1028 MHz Si539x devices support up to 12 different clock outputs, and are capable of meeting jitter requirements in emerging 112G SerDes slated for deployment in emerging 5G networks.
Silicon Labs has expanded its line of Si539x jitter attenuators with a fully integrated reference, allowing the devices to address reference clock requirements of 100G to 800G network designs. The 100 Hz to 1028 MHz Si539x devices support up to 12 different clock outputs, and are capable of meeting the jitter requirements of emerging 112G SerDes slated for deployment in emerging 5G network infrastructure applications.
The Si539x jitter attenuators are expected to be used with Ethernet switch ASICs, SoCs, FPGAs, and PHYs to help simplify circuit board design and layout. The integrated crystal reference provides high immunity to acoustic emissions, while also reducing PCB area requirements by more than 35 percent versus discrete timing solutions.
The Si539x jitter attenuators are available now, and can be evaluated on development boards priced at $299. Development is supported by Silicon Labs’ ClockBuilder Pro software.
More information can be found at www.silabs.com/timing.
