Cyber Physical Systems (CPS) are enabling technologies across multiple application domains to address societal and industrial challenges for autonomous and safe mobility, wellbeing and health, and sustainable production and smart manufacturing, among others. The applications to be deployed in these systems demand high-levels of performance operating with small power envelopes, while also entail the fulfillment of non-functional requirements including dependability, real-time response, resiliency, fault tolerance, security, and certifiability. In that regard, CPS are commonly developed using model-driven engineering (MDE) technologies, which facilitate the description of the functional and non-functional requirements inherited due to cyber/physical interaction characteristic of each domain.

Moreover, the use of energy-efficiency and highly parallel and heterogeneous embedded processor architectures, featuring many-core fabrics, GPUs or FPGA accelerators, can provide CPS with the required performance with low power consumption. These processor architectures incorporate parallel programming models in their software development kits to describe and exploit the parallelism of applications.

Unfortunately, MDE and parallel programming models are not compatible for a twofold reason: First, MDE lacks the mechanisms needed to effectively describe parallelism of applications; second, parallel programming models leave non-functional requirements aside.

AMPERE aims at developing a new generation of programming environments for low energy and highly parallel computing, capable of implementing advanced CPS. To that end, three different layers are considered. At the highest level, model-driven approaches must be extended to better capture the non-functional requirements of the system, including not only dependability, real-time response, resiliency, fault tolerance, security and certifiability, but also performance and energy-efficiency. This will allow tackling, in a holistic manner, the transformation of the model into parallel code optimized for the target architecture, including heterogeneous platforms featuring FPGA-based accelerators. At the middle level, the runtime system must ensure that the non-functional requirements described at the high-level are fulfilled by means of an adequate allocation of the parallel computation to the available computational resources, while it allows adapting to new working conditions, for example, through safe FPGA reconfiguration. Finally, at the lowest level, a hypervisor must guarantee safety and security requirements by means of isolation mechanisms, maintaining a highly efficient parallel execution.

The project will be evaluated using two real-world use cases from the automotive and railway domains. The automotive use-case consists of an Intelligent Predictive Cruise Control (PCC) CPS that aims at reducing fuel consumption. This use-case combines existing Adaptive Cruise Control (ACC) functionalities, together with information from the electronic horizon, including topographical data

like curvature, inclines or speed limits calculated through Traffic Sign Recognition (TSR) mechanisms based on deep neural networks techniques. The railway use-case consists of an Obstacle Detection and Avoidance System (ODAS) that aims at improving the safety levels of the Light Rail Transit (LRT) transportation system. This use-case incorporates two components: a Sensor Data Fusion (SDF) in charge of first collecting large mass of raw data from multiple advanced sensors installed in the tram vehicle, and then processing this data through deep learning technologies; and an AI Analytics component in charge of identifying and tracking objects along the tramway infrastructure, and extracting knowledge to be displayed to the tram driver, both using machine learning and deep learning techniques.

The AMPERE H2020 project started in January 2020 and has a duration of 36 months. For more information, please visit: http://ampere-euproject.eu/.

About the Author

Eduardo Quiñones is a senior researcher in the Department of Computer Science at the Barcelona Supercomputing Center (BSC). He received his Ph.D. in computer science from the Universitat Politècnica de Catalunya (UPC) in Barcelona. His research interests are strongly tied to next generation industry requirements for critical real-time systems spanning highly parallel heterogeneous processor architecture (incorporating many-core and DSP fabrics, GPUs, FPGA-based devices), parallel programming models, operating system and compiler designs.